This application is based on and hereby claims priority to PCT Application No. PCT/DE00/01249 filed on Apr. 20, 2000 and German Application No. 199 18 385.6 filed Apr. 22, 1999 in Germany, the contents of which are hereby incorporated by reference.
The present invention relates to a method and a circuit arrangement for regulating the signal level fed to an analog/digital converter.
According to the current state of the art, radio-frequency receivers (RF receivers) operate in analog mode in the RF receiving part. A received signal is only digitized after it has been mixed down into the baseband or an intermediate frequency. Since the RF input range may be very great on account of the different distances from the transmitter, the received signal must be normalized before further processing, in particular before its digitization. For this purpose, what are known as AGC (Automatic Gain Control) circuits are used, the task of which is to regulate the signal level fed to the analog/digital converter (A/D converter), provided in the receiver for digitization,in such a way that the A/D converter is not overloaded. Since the AGC circuit cannot operate at a rate allowing for the fast-fading effects occurring in the mobile radio sector, a safety reserve must be provided between the setpoint value assigned to the AGC circuit and the maximum value which can be converted by the A/D converter, so that the signal to be converted covers the entire operating range of the A/D converter minus the safety reserve. The safety reserve should be set to a margin allowing compensation for brief received signal peaks within the time constant of the controller used in the AGC circuit. Depending on the application, for example in the case of cordless digital telephones, the safety reserve may be 75% of the workable control range of the A/D converter, it being possible to accept a brief overloading of the A/D converter.
Both AGC circuits upstream of the A/D converter and AGC circuits downstream of the A/D converter are known variants. AGC circuits which are arranged downstream of the A/D converter have the advantage that no adjustment has to be carried out between the input level of the A/D converter and the input level of the AGC circuit.
DE 43 19 376 C1 discloses a method and a circuit arrangement for the analog/digital conversion of signals with different signal levels, in which the output signal of the analog/digital converter is monitored by a logical circuit module which is connected to the output of the analog/digital converter and in which the signal level fed to the analog/digital converter is set by the logical circuit module in dependence on the result of the monitoring in such a way that the signal level of the output signal remains within a certain range.
In FIG. 4, an example of an RF receiver with a known AGC circuit arranged downstream of the A/D converter is represented. A received or input signal is fed to the RF receiving part 2 of the RF receiver via an antenna 1. As already mentioned, the RF receiving part 2 operates in analog mode. The analog received signal is therefore fed for digitization to an A/D converter 4, the input signal level of which is regulated by a closed-loop control circuit, the closed-loop control circuit comprising a variable-gain amplifier 3, which is arranged between the RF receiving part 2 and the A/D converter 4. The A/D converter 4 shown in FIG. 4 is an 8-bit A/D converter, the 8-bit output value of which is fed to a unit 5, which calculates the absolute value of the signal value supplied by the A/D converter. The absolute value determined in this way is fed with a negative algebraic sign to an adder 6, which also receives a setpoint assignment SP, so that with the aid of the adder 6 the setpoint value SP is compared with the calculated absolute value and, in dependence on the result of the comparison, an adjustment signal for the amplifier 3 is generated, the adjustment signal being generated according to FIG. 4 by combination of two subsignals with the aid of an adder 9. The first subsignal is supplied by a unit 7, which integrates and scales the differential signal fed to it, while the second subsignal is supplied by a low-pass filter of the first order (LP) 8, which likewise additionally scales the differential signal fed to it. The unit 7 consequently represents the integral-action component of a PI controller, while the unit 8 represents the proportional-action component of the PI controller. With the aid of the closed-loop control circuit formed in this way, the input gain of the A/D converter 4 is regulated in such a way that the absolute value of the output signal of the A/D converter 4 always remains within a certain range, or approaches the setpoint value SP within a certain time.
One aspect of the present invention is based on the object of providing a novel method and a novel circuit arrangement for regulating the signal level fed to an analog/digital converter, it being intended for this method and circuit arrangement to make it possible for the signal level fed to the analog/digital converter to be regulated in the simplest way possible. In particular, the circuit arrangement is intended to require only a minimal number of components.
One aspect of the invention is based on the premise that the received signal in digital radio systems, such as for example in CDMA (Code Division Multiple Access) systems, is to correspond over time to a certain random distribution, irrespective of the information. Therefore, it is presumed that it is adequate to arrange the regulating of the signal level fed to the A/D converter in such a way, that, over a certain period of time, only a certain number of output signals of the A/D converter lie above a certain normalized signal level. This can be monitored by measuring the probability of change or the rate of change of the output signal of the A/D converter.
In particular, it is assumed that it is adequate to regulate the probability with which the information of a certain bit of the output signal of the A/D converter changes in such a way that it always lies within a certain range and does not exceed a predetermined limit value. This is possible since the output bits of the A/D converter correspond to certain thresholds, which occur more often with the modulo factor of their significance. For this purpose, one of the more-significant bits of the output signal of the A/D converter is advantageously monitored.
The probability with which the monitored output signal of the A/D converter changes must be less than 50%. The stability of the system is all the better, however, the smaller this limit value is. If, however, the limit value is chosen to be too small, under some circumstances not all the bits of the A/D converter are used and consequently system resources are wasted. A limit value of 25% has been found to be advantageous, since this value, represents a good compromise between the requirements mentioned above. This limit value is therefore advantageously used as the set point assignment for the regulating of the input signal level of the A/D converter, i.e. the input signal level of the A/D converter is regulated in such a way that the monitored output bit of the A/D converter is changed on average over time at most with a probability of 25%, i.e. every four sampled values. In the case of an 8-bit A/D converter, for example, the probability of change or rate of change of the sixth bit can consequently be regulated on the basis of 25%.
The principle described above makes it possible to construct an AGC circuit with a minimal number of components, which are moreover inexpensive. This results from the fact that regulating is not based on a specific output value of the A/D converter, but on the rate of change or probability of change of the A/D converter. The AGC circuit may be constructed in particular in such a way that it relates the change of the output signal of the A/D converter, in particular the change of a certain output bit, to the progression of time. If a small rate of change is measured in this way, the input gain of the A/D converter is increased by a corresponding regulating circuit, or in the other case it is reduced.